Error Generator: Only Single Bits

High-speed USB 2.0 to CAN/LIN Interface
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bm_kamath
Posts: 6
Joined: Fri 27. Mar 2015, 19:05

Error Generator: Only Single Bits

Post by bm_kamath » Thu 18. May 2017, 14:34

Hi Gunnar,

I have couple of questions:
  • For some of my experiments , i wanted to destroy the "Single Bit" in the farme without inducing a 6 dominant bits. Is there any way to do that ?
  • Also is there any way to selectively make the Bit dominant /recessive ?
Regards
bm_kamath
Last edited by K.Wagner on Thu 18. May 2017, 15:12, edited 2 times in total.
Reason: Formatted in a list for better reading

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G.Bohlen
Hardware Development
Hardware Development
Posts: 46
Joined: Wed 22. Sep 2010, 21:38

Re: Error Generator: Only Single Bits

Post by G.Bohlen » Thu 18. May 2017, 15:49

Hello,

it is not possible to modify only a single bit.
The module always generates a sequence of 6 dominant bits, starting at the defined bit position. If there were already 5 dominant bits straight bevore the defined position, the CAN nodes will detect a CAN-error after the first of the 6 dominant bits, and there will be a total of 11 dominant bits visible on the bus.

Regards, Gunnar Bohlen

bm_kamath
Posts: 6
Joined: Fri 27. Mar 2015, 19:05

Re: Error Generator: Only Single Bits

Post by bm_kamath » Thu 25. May 2017, 10:51

Thanks Gunnar for the clarification ...

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