PEAK-System Forum

Hello,

we're using the PCAN-miniPCIe Card to connect a Tegra K1(running Linux 4 Tegra) to the CAN Bus. Sending and Recieving CAN Frames works just fine. But we're looking for a way to monitor the CAN Frames before they are processed by Linux. The idea is to read the Recieve FIFO and TX Buffer directly out of the internal RAM of the CAN Controller. According to the Data Sheet of the SJA1000 this should be possible. But reading out the internal RAM does not seem to working. I just get the registers repeated all over again. Am I missing something or am I doing it wrong?

Here is the part of the code I'm using to read all the registers, including parts of the internal RAM:

Code: Select all

static u8 read_reg(int port)
{
    return readb(reg_base + (port << 2));
}

static int readCAN_init(void)
{
    printk(KERN_ALERT "Init readCAN module\n");
    
    pdev = pci_get_device(PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, pdev);
    
    if(!pdev)
    {
        printk(KERN_ALERT "PCI device can not be found\n");
    } else {
        reg_base = pci_iomap(pdev, 1, 0x400 * 2);

	for(i = 0; i < 96; i++){
		printk(KERN_DEBUG "BYTE%u: %x \n", i, read_reg(i));
	} 
    } 
    return 0;
}

Here is the output:

Code: Select all

[   86.083452] BYTE0: 0 
[   86.083456] BYTE1: 0 
[   86.083460] BYTE2: d 
[   86.083464] BYTE3: 1 
[   86.083467] BYTE4: 7f 
[   86.083471] BYTE5: 0 
[   86.083474] BYTE6: 3 
[   86.083478] BYTE7: 9c 
[   86.083482] BYTE8: 1a 
[   86.083485] BYTE9: 0 
[   86.083489] BYTE10: 0 
[   86.083493] BYTE11: 0 
[   86.083496] BYTE12: 0 
[   86.083500] BYTE13: 60 
[   86.083503] BYTE14: 0 
[   86.083507] BYTE15: 0 
[   86.083511] BYTE16: 4 
[   86.083514] BYTE17: 22 
[   86.083518] BYTE18: 20 
[   86.083522] BYTE19: 11 
[   86.083525] BYTE20: 22 
[   86.083529] BYTE21: 33 
[   86.083532] BYTE22: 44 
[   86.083536] BYTE23: 4 
[   86.083539] BYTE24: 22 
[   86.083543] BYTE25: 20 
[   86.083547] BYTE26: 11 
[   86.083550] BYTE27: 22 
[   86.083554] BYTE28: 33 
[   86.083557] BYTE29: 2 
[   86.083561] BYTE30: 0 
[   86.083564] BYTE31: c7 
[   86.083568] BYTE32: 0 
[   86.083571] BYTE33: 0 
[   86.083575] BYTE34: d 
[   86.083579] BYTE35: 1 
[   86.083582] BYTE36: 7f 
[   86.083586] BYTE37: 0 
[   86.083589] BYTE38: 3 
[   86.083593] BYTE39: 9c 
[   86.083596] BYTE40: 1a 
[   86.083600] BYTE41: 0 
[   86.083604] BYTE42: 0 
[   86.083607] BYTE43: 0 
[   86.083611] BYTE44: 0 
[   86.083614] BYTE45: 60 
[   86.083618] BYTE46: 0 
[   86.083621] BYTE47: 0 
[   86.083625] BYTE48: 0 
[   86.083628] BYTE49: 0 
[   86.083632] BYTE50: 0 
[   86.083636] BYTE51: 0 
[   86.083639] BYTE52: ff 
[   86.083643] BYTE53: ff 
[   86.083646] BYTE54: ff 
[   86.083650] BYTE55: ff 
[   86.083653] BYTE56: 0 
[   86.083657] BYTE57: 0 
[   86.083660] BYTE58: 0 
[   86.083664] BYTE59: 0 
[   86.083668] BYTE60: 0 
[   86.083671] BYTE61: 2 
[   86.083675] BYTE62: 0 
[   86.083678] BYTE63: c7 
[   86.083682] BYTE64: 0 
[   86.083686] BYTE65: 0 
[   86.083689] BYTE66: d 
[   86.083693] BYTE67: 1 
[   86.083696] BYTE68: 7f 
[   86.083700] BYTE69: 0 
[   86.083703] BYTE70: 3 
[   86.083707] BYTE71: 9c 
[   86.083711] BYTE72: 1a 
[   86.083714] BYTE73: 0 
[   86.083718] BYTE74: 0 
[   86.083721] BYTE75: 0 
[   86.083725] BYTE76: 0 
[   86.083729] BYTE77: 60 
[   86.083732] BYTE78: 0 
[   86.083736] BYTE79: 0 
[   86.083739] BYTE80: 0 
[   86.083743] BYTE81: 0 
[   86.083746] BYTE82: 0 
[   86.083750] BYTE83: 0 
[   86.083753] BYTE84: ff 
[   86.083757] BYTE85: ff 
[   86.083761] BYTE86: ff 
[   86.083764] BYTE87: ff 
[   86.083768] BYTE88: 0 
[   86.083771] BYTE89: 0 
[   86.083775] BYTE90: 0 
[   86.083779] BYTE91: 0 
[   86.083782] BYTE92: 0 
[   86.083786] BYTE93: 2 
[   86.083789] BYTE94: 0 
[   86.083793] BYTE95: c7 
[   89.921920] Remove readCAN module

Linux4Tegra is based in Ubuntu 14.04 and running Kernel 3.10.40

Thanks and best regards

Hello,

First of all, how do you "send and receive the CAN Frames"? Are you using the mainline driver peak_pci or did you cross-compile the "pcan" driver?

Regards,

Stéphane

Hello,

I'm using the mainline driver peak_pci and use cansend and candump from the can-utils package to test the communication.

Hello,

First of all, your read_reg() function is only able to read into the 1st SJA1000. Your reg_base is actually a base address for both channels/SJA1000 address spaces. Accessing 2nd SJA1000 should be done from reg_base + 0x400.

Next, reading a SJA1000 address space means reading its internal registers. You have to read the SJA1000 data sheet to know which register is at which address. For example, the status register of the SJA1000 is at offset 0x02. Thus, when you call read_reg(0x02) then you read the content of the status register of the 1st SJA1000 (actually your "BYTE3" which is 0x0d, which indicates "Transmission Complete + Receive Buffer full").

Regards,

Stéphane

Hello Stéphane,

thanks for your answer.

S.Grosjean wrote: First of all, your read_reg() function is only able to read into the 1st SJA1000. Your reg_base is actually a base address for both channels/SJA1000 address spaces. Accessing 2nd SJA1000 should be done from reg_base + 0x400.

We've just can0 connected to the CAN-BUS. The way I understand it's one SJA1000 for each channel. That's why I just read the first one.

Next, reading a SJA1000 address space means reading its internal registers. You have to read the SJA1000 data sheet to know which register is at which address. For example, the status register of the SJA1000 is at offset 0x02. Thus, when you call read_reg(0x02) then you read the content of the status register of the 1st SJA1000 (actually your "BYTE3" which is 0x0d, which indicates "Transmission Complete + Receive Buffer full").

I've read the SJA1000 data sheet and application notes. Reading the internal registers up to can address 31 seems to be fine. By reading the receive puffer starting at can addresse 16 I get first of the messages I sent beforhand as a test and the message counter at can address 29 also has the right value (I've sent 2 messages). The problem starts at can adress 32 where the internal RAM, containing the recieve FIFO and transmit buffer, should start according to the data sheet. I don't get the FIFO but just some gibberish output which seems to be the internal registers repeated all over again. But it's the receive fifo and the transmit buffer I actually want to read and the application notes say it's possible to access the RAM of the SJA1000 directly. So I don't understand why it's not working and I'm wondering what I'm doing wrong.

Regards,

Selina

Hi,

You should find what you need in the Kernel code directly:

In this location http://lxr.free-electrons.com/source/dr ... n/sja1000/ you'll find all what is about SJA1000 drivers.

The core of the SJA1000 drivers is sja1000.c. The specific part of each manufacturer is contained in all the other files. For example, you'll find our interface into peak_pci.c.

Since I don't really know whether and/or how you initialize the SJA1000 and the PITA, I strongly advice you to have a deep look to these two files first.

Regards,

Stéphane

Hello,

ok, I'll look into it.
Thanks for your help.

Regards,

Selina

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