PCAN-miniPCIe compatible with SJA1000 driver

[the_summer]

Hello,

we are considering buying the PCAN-miniPCIe as an extension for an x86-based system. However, our main computer runs the RTEMS operating system.
In order to use the device we need need to write a new or port an existing driver.
As you state the FPGA devices are SJA1000 compatible we would kindly ask to answer the following questions so we can guess the necessary workload for driver development:

- How is the SJA1000 addressed via the PCI bus? Are the SJA registers just the offset from the PCI Base address register?
- How do we change from reset mode to operating mode and vice versa using PCI?
- Is the support of special PCI features like msi necessary for controlling the chip?
- Are both SJA1000 devices realised as 2 separate identifcal PCI devices?
- Are there any further considerations we need to take into account for driver development?

Thank you very much for your help.

[PEAK-Support]

please take a look into our LINUX driver - there you find all information you need

[jspring]

Hi the_summer: Did you ever figure out the answers to your questions? The documentation referred to by Peak support is for Windows and Linux. We are using QNX, so we also want to know how to address the SJA registers. QNX can find the RTD carrier board, and it gives the base addresses for the PCI configuration registers, but I'm in the dark about the Peak cards. Do you have any hints? Thanks!

[the_summer]

Hi jspring,

Our project has been delayed. So we don't have the hardware yet, but it is ordered.
But from experience with other PCI cards, I would expect that the SJA1000 registers are mapped into memory.

For normal computers the addresses should be assigned by the BIOS. To get the addresses you have to read out the Base Address Register (BAR) in PCI configuration space.

I haven't checked in detail if these things have changed much in PCIe, but I would expect not.
I also looked at the Linux driver back in the day, but it is not that easy to read. So my idea was to check if a simple embedded driver exists where I only need to change the access functions for the registers.

[P.Steil]

Hello,

here are some hints for the PCI/PCIe platforms (SJA1000 based):
- There are two BARs

- BAR 0 is for a PCI to parallel bridge
This is from legacy (original) PCI chipset based on a PCI chip for ISDN networks.
Here are a few registers for interrupt enable and status

- BAR 1 is for the CAN Controllers
All CANs are located here (memory space). CAN1 is at BAR1. All additional CANs
will use an offset of 0x400 to the next controller. Each byte of a SJA1000 register
is mapped into the LSB of a 32 bit DWORD. So from each DWORD only the LSB is used
here.

- MSI is only available on PCIe FPGA based devices.

- PCI multi-function devices is not supported. CANs will use offset on BAR1, see above


Hope this will help to understand linux code more easy.

Regards

[the_summer]

Sorry for digging up this old thread, but it has become relevant for us again.

I have a question regarding the BAR 0:

In the Linux driver I see that there are some registers written to. Is this always necessary even for newer cards?
Or could we use our custom SJA1000 driver operating on BAR 1 and be done?

[M.Heidemann]

Hello,

You will still need BAR 0 for the interrupt enable register, etc.

However the registers for "MISC" and "GPIOICR" are not used anymore and can be
omitted.

Best Regards

Marvin

[the_summer]

Hi Marvin,

Thank you for the fast reply. It helped understanding the interrupt code of the driver.
Do you have a name of the PITA device, so I can search for the according data sheet with the register descriptions?

Without any reference I am left with some kind of cargo-cult programming, which I usually try to avoid.

Best regards,

Jan

[M.Heidemann]

Hello,

We cannot provide further information regarding this.

All necessary information is available in the soruce code for the driver,
the aforementioned registers are also defined there.

Best Regards

Marvin